參數(shù)資料
型號(hào)： MT46V16M4
廠商： Micron Technology, Inc.
英文描述： 4 Meg x 4 x 4 banks DDR SDRAM(4 M x 4 x 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述： 4梅格× 4 × 4銀行DDR SDRAM內(nèi)存（四米× 4 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 38/69頁(yè)
文件大?。?/td> 2369K
代理商： MT46V16M4
38
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKE
n-1
CKE
n
L
CURRENT STATE
Power-Down
Self Refresh
Power-Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
COMMA ND
n
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Truth Table 3
A CTION
n
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
NOTES
L
L
H
5
H
L
H
H
NOTE:
1. CKE
n
is the logic state of CKE at clock edge
n
; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge
n
.
3. COMMAND
is the command registered at clock edge
n
, and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the
t
XSR period. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V16M8 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
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