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參數(shù)資料
| 型號： | MSC7118VF1200 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 300 MHz, OTHER DSP, PBGA400 |
| 封裝： | 17 X 17 MM, MAPBGA-400 |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 1528K |
| 代理商： | MSC7118VF1200 |
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MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Hardware Design Considerations
Freescale Semiconductor
54
3.5.3
General Routing
The general routing considerations for the DDR are as follows:
All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
Minimize data bit jitter by trace matching.
3.5.4
Routing Clock Distribution
The DDR clock distribution considerations are as follows:
DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
For route traces as for any other differential signals:
— Maintain proper difference pair spacing.
— Match pair traces within 25 mm.
Match all clock traces to within 100 mm.
Keep all clocks equally loaded in the system.
Route clocks on inner critical layers.
3.5.5
Data Routing
The DDR data routing considerations are as follows:
Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
Take care to match trace lengths, which is extremely important.
To make trace matching easier, let adjacent groups be routed on alternate critical layers.
Pin swap bits within a byte group to facilitate routing (discrete case).
Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the design for readjustments as needed.
DDR data group separation:
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC7118VF1200,
MSC7118VM1200,
MSC711XADS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC7118VM1200 | 功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC7119 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7119_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7119VF1200 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC FASTSTAR DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MSC7119VM1200 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC FASTSTAR DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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