參數(shù)資料
型號(hào): MSC7118VF1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, MAPBGA-400
文件頁數(shù): 37/60頁
文件大?。?/td> 1528K
代理商: MSC7118VF1200
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Hardware Design Considerations
Freescale Semiconductor
42
3.2.2.2
Case 2
The power-up sequence is as follows:
1.
Turn on the VDDIO (3.3 V) supply first.
2.
Turn on the VDDC (1.2 V) and VDDM (2.5 V) supplies simultaneously (second).
3.
Turn on the VREF (1.25 V) supply last (third).
Note:
Make sure that the time interval between the ramp-up of VDDIO and VDDC/VDDM is less than 10 ms.
The power-down sequence is as follows:
1.
Turn off the VREF (1.25 V) supply first.
2.
Turn off the VDDM (2.5 V) supply second.
3.
Turn off the VDDC (1.2 V) supply third.
4.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 27 for relative timing for Case 2.
Figure 27. Voltage Sequencing Case 2
Time
Vo
lt
a
g
e
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC7118VF1200,
MSC7118VM1200,
MSC711XADS
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相關(guān)代理商/技術(shù)參數(shù)
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