參數(shù)資料
型號(hào): MSC7118VF1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, MAPBGA-400
文件頁(yè)數(shù): 43/60頁(yè)
文件大小: 1528K
代理商: MSC7118VF1200
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Hardware Design Considerations
Freescale Semiconductor
48
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I
2C module.
Basic power consumption by each module is assumed to be the same and is computed by using the following equation which
assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100 MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)
2 × 150 MHz × 10–3 = 4.32 mW per peripheral
Eqn. 6
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7118
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Eqn. 7
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
Eqn. 8
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)
2 × 300 MHz × 10–3 mW
Eqn. 9
pin activity value = (active data lines
× % activity × % data switching) + (active address lines × % activity)
Eqn. 10
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
2
× 300 × 10–3) = 326.3 mW
Eqn. 11
3.3.4
External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz,
which yields:
PIO = 20 pF × (3.3 V)
2
× 25 MHz × 10–3 = 5.44 mW per I/O line
Eqn. 12
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Note:
The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
3.3.5
Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC7118VF1200,
MSC7118VM1200,
MSC711XADS
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參數(shù)描述
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