參數(shù)資料
型號: MSC7110VM800
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 顯示控制器
英文描述: FLUORESCENT DSPL CTRL, PBGA400
封裝: 17 X 17 MM, LEAD FREE, BGA-400
文件頁數(shù): 49/56頁
文件大?。?/td> 702K
代理商: MSC7110VM800
Ordering Information
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
53
3.6
Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7110
device. Following are guidelines for signal groups and configuration settings:
Clock and reset signals.
SWTE is used to configure the MSC7110 device and is sampled on the deassertion of PORESET, so it should be
tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After
PORESET
, this signal can be left floating.
BM[0–1] configure the MSC7110 device and are sampled until PORESET is deasserted, so they should be tied to
VDDIO or GND either directly or through pull-up or pull-down resistors.
HRESET should be pulled up.
Interrupt signals. When used, IRQ pins must be pulled up.
HDI16 signals.
— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the HRESET signal as the enable.
— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.
General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
Other signals.
—The TEST0 pin must be connected to ground.
—The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT
pins, and DBREQ to HRRQ.
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part
Supply
Voltage
Package Type
Pin
Count
Core
Frequency
(MHz)
Solder Spheres
Order Number
MSC7110
(mask
1L44X
1.2 V core
2.5 V mem.
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
200
Lead-free
MSC7110VM800
Lead-bearing
MSC7110VF800
MSC7110
(mask
1M88B)
1.2 V core
2.5 V mem
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
266
Lead-free
MSC7110VM1000
Lead-bearing
MSC7110VF1000
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
相關(guān)PDF資料
PDF描述
MSC7110VM1000 FLUORESCENT DSPL CTRL, PBGA400
MSC7118VF1200 0-BIT, 300 MHz, OTHER DSP, PBGA400
MSC8101M1250F 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
MSC8101M1500F 64-BIT, 75 MHz, OTHER DSP, PBGA332
MSC8101VT1250F 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
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