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參數(shù)資料
| 型號： | MSC7110VM800 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | FLUORESCENT DSPL CTRL, PBGA400 |
| 封裝： | 17 X 17 MM, LEAD FREE, BGA-400 |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MSC7110VM800 |
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Specifications
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
25
2.5.4.2
DDR DRAM Output AC Timing Specifications
Table 19 and Table 20 list the output AC timing specifications and measurement conditions for the DDR DRAM interface.
Table 19. DDR DRAM Output AC Timing
No.
Parameter
Symbol
Min
Max
Unit
Mask Set
1L44X
Mask Set
1M88B
200
CK cycle time, (CK/CK crossing)1
100 MHz (DDR200)
133 MHz (DDR266)
tCK
10
Not applicable
1.0
7.52
—
ns
204
An/RAS/CAS/WE/CKE output setup with respect to
CK
tDDKHAS
0.5
× tCK – 2250
0.5
× tCK – 1000
—
ps
205
An/RAS/CAS/WE/CKE output hold with respect to CK
tDDKHAX
0.5
× tCK – 1250
0.5
× tCK – 1000
—
ps
206
CSn output setup with respect to CK
tDDKHCS
0.5
× tCK – 2250
0.5
× tCK – 1000
—
ps
207
CSn output hold with respect to CK
tDDKHCX
0.5
× tCK – 1250
0.5
× tCK – 1000
—
ps
208
CK to DQSn2
tDDKHMH
–600
600
ps
209
Dn/DQMn output setup with respect to DQSn3
tDDKHDS,
tDDKLDS
0.25
× tMCK –
1050
0.25
× tCK – 750
—
ps
210
Dn/DQMn output hold with respect to DQSn3
tDDKHDX,
tDDKLDX
0.25
× tCK – 1050
0.25
× tCK – 750
—
ps
211
DQSn preamble start4
tDDKHMP
–0.25
× tCK
–0.25
× tCK
—ps
212
DQSn epilogue end5
tDDKHME
–600
600
ps
Notes:
1.
All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
2.
tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 410 ps before
the CK/CK crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval
from –410 to +677 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3.
Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4.
Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5.
All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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