參數資料
型號: MSC7110VM800
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 顯示控制器
英文描述: FLUORESCENT DSPL CTRL, PBGA400
封裝: 17 X 17 MM, LEAD FREE, BGA-400
文件頁數: 28/56頁
文件大?。?/td> 702K
代理商: MSC7110VM800
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
34
2.5.8
UART Timing
2.5.9
EE Timing
Figure 19 shows the signal behavior of the EE pin.
Table 24. UART Timing
No.
Characteristics
Expression
Mask Set
1L44X
Mask Set
1M88B
Unit
Min
Max
Min
Max
Internal bus clock (APBCLK)
FCORE/2
100
133
MHz
Internal bus clock period (1/APBCLK)
TAPBCLK
10.0
7.52
ns
400
URXD and UTXD inputs high/low duration
16
× TAPBCLK
160.0
120.3
ns
401
URXD and UTXD inputs rise/fall time
5
5
ns
402
UTXD output rise/fall time
5
5
ns
Figure 17. UART Input Timing
Figure 18. UART Output Timing
Table 25. EE0 Timing
Number
Characteristics
Type
Min
65
EE0 input to the core
Asynchronous
4 core clock periods
66
EE0 output from the core
Synchronous to core clock
1 core clock period
Notes:
1.
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2.
Configure the direction of the EE pin in the EE_CTRL register (see the SC1400 Core Reference Manual for details.
3.
Refer to Table 15 for details on EE pin functionality.
Figure 19. EE Pin Timing
UTXD, URXD
400
inputs
400
401
UTXD output
402
EE0 in
65
EE0 out
66
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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