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| 型號： | MSC7110VM800 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | FLUORESCENT DSPL CTRL, PBGA400 |
| 封裝： | 17 X 17 MM, LEAD FREE, BGA-400 |
| 文件頁數(shù)： | 48/56頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MSC7110VM800 |
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MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Hardware Design Considerations
Freescale Semiconductor
52
3.5.3
General Routing
The general routing considerations for the DDR are as follows:
All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
Minimize data bit jitter by trace matching.
3.5.4
Routing Clock Distribution
The DDR clock distribution considerations are as follows:
DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
For route traces as for any other differential signals:
— Maintain proper difference pair spacing.
— Match pair traces within 25 mm.
Match all clock traces to within 100 mm.
Keep all clocks equally loaded in the system.
Route clocks on inner critical layers.
3.5.5
Data Routing
The DDR data routing considerations are as follows:
Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
Take care to match trace lengths, which is extremely important.
To make trace matching easier, let adjacent groups be routed on alternate critical layers.
Pin swap bits within a byte group to facilitate routing (discrete case).
Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the design for readjustments as needed.
DDR data group separation:
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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