![](http://datasheet.mmic.net.cn/30000/MR80C52CXXX-20SCR_datasheet_2377250/MR80C52CXXX-20SCR_947.png)
947
32142D–06/2013
ATUC64/128/256L3/4U
The flash programming time is now
:
Fix/Workaround
None.
4.
Power Manager
5.
Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
6.
Sleepwalking in idle and frozen sleep mode will mask all other PB clocks
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
4.
Unused PB clocks are running
Three unused PBA clocks are enabled by default and will cause increased active power
consumption.
Fix/Workaround
Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register.
38.5.3
SCIF
1.
The RC32K output on PA20 is not always permanently disabled
The RC32K output on PA20 may sometimes re-appear.
Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
to properly disable it:
- Run the CPU on RCSYS
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.
2.
PLL lock might not clear after disable
Table 38-1.
Flash Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TFPP
Page programming time
fCLK_HSB= 50MHz
7.5
ms
T
FPE
Page erase time
7.5
TFFP
Fuse programming time
1
TFEA
Full chip erase time (EA)
9
TFCE
JTAG chip erase time
(CHIP_ERASE)
fCLK_HSB= 115kHz
250