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型號(hào)：	MQ83C154XXX-30P883D
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	165/963頁(yè)
文件大小：	11933K
代理商：	MQ83C154XXX-30P883D

32142D–06/2013

ATUC64/128/256L3/4U

used in Shutdown mode, PINSEL must be written to one, and XIN32_2 and XOUT32_2 must be

PLL Operation

Rev: 1.1.0.0

The device contains one Phase Locked Loop (PLL), which is controlled by the Phase Locked

Loop Interface (PLLIF). The PLL is disabled by default, but can be enabled to provide high fre-

quency source clocks for synchronous or generic clocks. The PLL can use different clock

sources as reference clock, please refer to the “PLL Clock Sources” table in the SCIF Module

Configuration section for details. The PLL output is divided by a multiplication factor, and the

PLL compares the phase of the resulting clock to the reference clock. The PLL will adjust its out-

put frequency until the two compared clocks phases are equal, thus locking the output frequency

to a multiple of the reference clock frequency.

When the PLL is switched on, or when changing the clock source or multiplication factor for the

PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital

logic is automatically masked when the PLL is unlocked, to prevent the connected digital logic

from receiving a too high frequency and thus become unstable.

The PLL can be configured by writing the PLL Control Register (PLLn). To prevent unexpected

writes due to software bugs, write access to the PLLn register is protected by a locking mecha-

nism, for details please refer to the UNLOCK register description.

Figure 14-1. PLL with Control Logic and Filters

Enabling the PLL

Before the PLL is enabled it must be set up correctly. The PLL Oscillator Select field (PLLOSC)

selects a source for the reference clock. The PLL Multiply Factor (PLLMUL) and PLL Division

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