![](http://datasheet.mmic.net.cn/30000/MR80C52CXXX-20SCR_datasheet_2377250/MR80C52CXXX-20SCR_615.png)
615
32142D–06/2013
ATUC64/128/256L3/4U
25. Pulse Width Modulation Controller (PWMA)
Rev: 2.0.1.0
25.1
Features
Left-aligned non-inverted 12-bit PWM
Common 12-bit timebase counter
– Asynchronous clock source supported
– Spread-spectrum counter to allow a constantly varying duty cycle
Separate 12-bit duty cycle register per channel
Synchronized channel updates
– No glitches when changing the duty cycles
Interlinked operation supported
– Up to 32 channels can be updated with the same duty cycle value at a time
– Up to 4 channels can be updated with different duty cycle values at a time
Interrupt on PWM timebase overflow
Incoming peripheral events supported
– Pre-defined channels support incoming (increase/decrease) peripheral events from the
Peripheral Event System
– Incoming increase/decrease event can either increase or decrease the duty cycle by one
One output peripheral event supported
– Connected to channel 0 and asserted when the common timebase counter is equal to the
programmed duty cycle for channel 0
Output PWM waveforms
– Support normal waveform output for each channel
– Support composite waveform generation (XOR’ed) for each pair channels
Open drain driving on selected pins for 5V PWM operation
25.2
Overview
The Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM)
channels. The number of channels is specific to the device. Each channel controls one square
output PWM waveform. Characteristics of the output PWM waveforms such as period and duty
cycle are configured through the user interface. All user interface registers are mapped on the
peripheral bus.
The duty cycle value for each channel can be set independently, while the period is determined
by a common timebase counter (TC). The timebase for the counter is selected by using the allo-
cated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains
handshake and synchronizing logic to ensure that no glitches occur on the output PWM wave-
forms while changing the duty cycle values.
PWMA duty cycle values can be changed using two approaches, either an interlinked single-
value mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of
channels, up to 32 channels, can be updated simultaneously with the same value while the other
channels remain unchanged. There is also an interlinked multi-value mode, where the 8 least
significant bits of up to 4 channels can be updated with 4 different values while the other chan-
nels remain unchanged.
Some pins can be driven in open drain mode, allowing the PWMA to generate a 5 V waveform
using an external pullup resistor.