![](http://datasheet.mmic.net.cn/30000/MR80C52CXXX-20SCR_datasheet_2377250/MR80C52CXXX-20SCR_259.png)
259
32142D–06/2013
ATUC64/128/256L3/4U
Supply Monitor 3.3V Detection bit in the Interrupt Mask Register (IMR.SM33DET) is set. This bit
is set by writing a one to the corresponding bit in the Interrupt Enable Register (IER.SM33DET).
If SM33.CTRL is one, a POR will be generated when the voltage drops below the threshold. If
SM33.CTRL is two, the device will not be reset.
14.5.9.4
Factory calibration
After a reset the SM33.CALIB field is loaded with a factory defined value. This value is chosen
so that the nominal threshold value is 1.75V. The flash calibration is redone after any reset, and
the Flash Calibration Done bit in SM33 (SM33.FCD) is set before program execution starts in the
CPU.
Although it is not recommended to override default factory settings, it is still possible to override
the default value by writing to SM33.CALIB
14.5.10
Temperature Sensor
Rev: 1.0.0.0
The Temperature Sensor is connected to an ADC channel, please refer to the ADC chapter for
details. It is enabled by writing one to the Enable bit (EN) in the Temperature Sensor Configura-
tion Register (TSENS). The Temperature Sensor can not be calibrated.
Please refer to the Electrical Characteristics chapter for more details.
14.5.11
120MHz RC Oscillator (RC120M)
Rev: 1.1.0.0
The 120MHz RC Oscillator can be used as source for the main clock in the device, as described
in the Power Manager chapter. The oscillator can also be used as source for the generic clocks,
as described in Generic Clock section. The RC120M must be enabled before it is used as a
source clock. To enable the clock, the user must write a one to the Enable bit in the 120MHz RC
Oscillator Control Register (RC120MCR.EN), and read back the RC120MCR register until the
EN bit reads one. The clock is disabled by writing a zero to RC120MCR.EN. The EN bit must be
read back as zero before the RC120M is re-enabled. If not, undefined behavior may occur.
The oscillator is automatically disabled in certain sleep modes to reduce power consumption, as
described in the Power Manager chapter.
14.5.12
Backup Registers (BR)
Rev: 1.0.0.1
Four 32-bit backup registers are available to store values when the device is in Shutdown
mode. These registers will keep their content even when the VDDCORE supply and the internal
regulator supply voltage supplies are removed. The backup registers can be accessed by read-
ing from and writing to the BR0, BR1, BR2, and BR3 registers.
After writing to one of the backup registers the user must wait until the Backup Register Interface
Ready bit in tne Power and Clocks Status Register (PCLKSR.BRIFARDY) is set before writing to
another backup register. Writes to the backup register while PCLKSR.BRIFARDY is zero will be
discarded. An interrupt can be generated on a zero-to-one transition on PCLKSR.BRIFARDY if