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7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hard-
ware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog
Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE
must be set after each interrupt. This should however not be done within the interrupt service
routine itself, as this might compromise the safety-function of the Watchdog System Reset
mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.
Note:
1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.
Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 10-2.
Watchdog Timer Configuration
WDE
WDIE
Mode
Action on Time-out
1
0
Stopped
None
1
0
1
Interrupt Mode
Interrupt
1
0
System Reset Mode
Reset
111
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
0
x
System Reset Mode
Reset