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參數資料
| 型號： | MQ80C52TXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數： | 8/46頁 |
| 文件大?。?/td> | 4720K |
| 代理商： | MQ80C52TXXX-12SB |
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15
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
5.
Memories
This section describes the different memories in the ATtiny20. The device has two main memory areas, the program
memory space and the data memory space.
5.1
In-System Re-programmable Flash Program Memory
The ATtiny20 contains 2K byte on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR
instructions are 16 or 32 bits wide, the Flash is organized as 1024 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny20 Program Counter (PC) is 10
bits wide, thus capable of addressing the 1024 program memory locations, starting at 0x000. “Memory Programming” on
page 159 contains a detailed description on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since program memory can not be
accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address
0x4000 in data memory (see Figure 5-1 on page 15). Although programs are executed starting from address 0x000 in
program memory it must be addressed starting from 0x4000 when accessed via the data memory.
Internal write operations to Flash program memory have been disabled and program memory therefore appears to
firmware as read-only. Flash memory can still be written to externally but internal write operations to the program
memory area will not be succesful.
Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 11.
5.2
Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and the
Flash memory. See Figure 5-1 for an illustration on how the ATtiny20 memory space is organized.
Figure 5-1.
Data Memory Map (Byte Addressing)
The first 64 locations are reserved for I/O memory, while the following 128 data memory locations (from 0x0040 to
0x00BF) address the internal data SRAM.
0x0000 ... 0x003F
0x0040 ... 0x00BF
0x00C0 ... 0x3EFF
0x3F00 ... 0x3F01
0x3F02 ... 0x3F3F
0x3F40 ... 0x3F41
0x3F42 ... 0x3F7F
0x3F80 ... 0x3F81
0x3F82 ... 0x3FBF
0x3FC0 ... 0x3FC3
0x3FC4 ... 0x3FFF
0x4000 ... 0x47FF
0x4800 ... 0xFFFF
I/O SPACE
SRAM DATA MEMORY
(reserved)
NVM LOCK BITS
(reserved)
CONFIGURATION BITS
(reserved)
CALIBRATION BITS
(reserved)
DEVICE ID BITS
(reserved)
FLASH PROGRAM MEMORY
(reserved)
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