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ATtiny20 [DATASHEET]
8235E–AVR–03/2013
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in
one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while
achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny20 provides the following features:
2K bytes of in-system programmable Flash
128 bytes of SRAM
Twelve general purpose I/O lines
16 general purpose working registers
An 8-bit Timer/Counter with two PWM channels
A 16-bit Timer/Counter with two PWM channels
Internal and external interrupts
An eight-channel, 10-bit ADC
A programmable Watchdog Timer with internal oscillator
A slave two-wire interface
A master/slave serial peripheral interface
An internal calibrated oscillator
Four software selectable power saving modes
The device includes the following modes for saving power:
Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O
modules except the ADC
Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system
programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory
programmer.
The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and
evaluation kits.