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參數(shù)資料
| 型號： | MQ80C52TXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 4720K |
| 代理商： | MQ80C52TXXX-12SB |
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11
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space
must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one
when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a
subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from
subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer
and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using
SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of
SRAM. See Figure 5-1 on page 15.
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
Figure 4-5.
Single Cycle ALU Operation
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
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