32
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 8-7.
Watchdog Timer
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when
using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels
Table 8-1.
WDT Configuration as a Function of the Fuse Settings of WDTON
8.4.1
Procedure for Changing the Watchdog Timer Configuration
The sequence for changing configuration differs between the two safety levels, as follows:
8.4.1.1 Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any
restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog
Timer, the following procedure must be followed:
1.
Write the signature for change enable of protected I/O registers to register CCP
2.
Within four instruction cycles, in the same operation, write WDE and WDP bits
8.4.1.2 Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A protected change is
needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must
be followed:
1.
Write the signature for change enable of protected I/O registers to register CCP
2.
Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
WDTON
Safety Level
Initial State
How to Disable
How to Change Time-out
Unprogrammed
1
Disabled
Protected change sequence
No limitations
Programmed
2
Enabled
Always enabled
Protected change sequence
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUX