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參數(shù)資料
| 型號： | MPE603RRX300LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 418K |
| 代理商： | MPE603RRX300LX |
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MOTOROLA
EC603e Microprocessor Hardware Specifications (PID7t), Rev. 2.0
9
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
1.4.2.2 Input AC Specications
Table 7 provides the input AC timing specications for the PID7t as dened in Figure 2 and Figure 3.
Table 7. Input AC Timing Specifications1
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105 C
Num
Characteristic
200, 266,
300 MHz
Unit
Notes
Min
Max
10a
Address/data/transfer attribute inputs valid to SYSCLK (input setup)
2.5
ns
2
10b
All other inputs valid to SYSCLK (input setup)
3.5
ns
3
10c
Mode select inputs valid to HRESET (input setup) (for DRTRY,
QACK and TLBISYNC)
8
tsysclk 4, 5, 6, 7
11a
SYSCLK to address/data/transfer attribute inputs invalid (input hold)
1.0
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
ns
3
11c
HRESET to mode select inputs invalid (input hold) (for DRTRY,
QACK, and TLBISYNC)
0
ns
4, 6, 7
Notes:
1. Input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V
of the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/data/transfer attribute input signals are composed of the followingA[031], AP[03], TT[04],
TC[01], TBST, TSIZ[02], GBL, DH[031], DL[031], DP[07].
3. All other input signals are composed of the followingTS, ABB, DBB, ARTRY, BG, AACK, DBG,
DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of
the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode only. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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