參數(shù)資料
型號： MPE603RRX300LX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁數(shù)： 27/28頁
文件大?。?/td> 418K
代理商： MPE603RRX300LX
8
EC603e Microprocessor Hardware Specifications (PID7t), Rev. 2.0
MOTOROLA
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1. After fabrication, parts are sorted
by maximum processor core frequency as shown in Section 1.4.2.1, Clock AC Specications, and tested
for conformance to the AC specications for that frequency. Parts are sold by maximum processor core
frequency; see Section 1.9, Ordering Information.
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105 C
Num
Characteristic
200 MHz
266 MHz
300 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Processor frequency
80
200
150
266
180
300
MHz
1,6
VCO frequency
300
400
300
532
360
600
MHz
1
SYSCLK frequency
25
66.7
25
75
33.3
75
MHz
1
SYSCLK cycle time
13.3
40
13.3
40
13.3
30
ns
2,3
SYSCLK rise and fall time
2.0
2.0
2.0
ns
2
4
SYSCLK duty cycle measured at 1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
±150
±150
±150
ps
4
PID7t internal PLL-relock time
100
100
100
ms
3,5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[03] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[03] signal description in Section 1.8,
System Design Information, for valid PLL_CFG[03] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined)
must be under ±150 ps to guarantee the input/output timing of Section 1.4.2.2, Input AC Specications, and
Section 1.4.2.3, Output AC Specications.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the
power-on reset sequence. This specication also applies when the PLL has been disabled and subsequently
re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus
clocks after the PLL-relock time (100
ms) during the power-on reset sequence.
6. Operation below 150 MHz is supported only by PLL_CFG[03] = 0b0101. Refer to Section 1.8.1, PLL
Conguration for additional information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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