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參數(shù)資料
| 型號： | MPE603RRX300LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 418K |
| 代理商： | MPE603RRX300LX |
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MOTOROLA
EC603e Microprocessor Hardware Specifications (PID7t), Rev. 2.0
3
provides a three-state coherency protocol that supports the exclusive, modied, and invalid cache states.
This protocol is a compatible subset of the MESI (modied/exclusive/shared/invalid) four-state protocol and
operates coherently in systems that contain four-state caches. The PID7t supports single-beat and burst data
transfers for memory accesses, and supports memory-mapped I/O.
The PID7t uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface
compatibility with TTL devices.
1.2 Features
This section summarizes features of the PID7ts implementation of the PowerPC architecture. Major
features of the PID7t are as follows:
High-performance, superscalar microprocessor
As many as three instructions issued and retired per clock
As many as ve instructions in execution per clock
Single-cycle execution for most instructions
Four independent execution units and two register les
BPU featuring static branch prediction
A 32-bit IU
LSU for data transfer between data cache and GPRs
SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
Thirty-two GPRs for integer operands
High instruction and data throughput
Zero-cycle branch capability (branch folding)
Programmable static branch prediction on unresolved conditional branches
Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
A six-entry instruction queue that provides lookahead capability
Independent pipelines with feed-forwarding that reduces data dependencies in hardware
16-Kbyte data cachefour-way set-associative, physically addressed; LRU replacement
algorithm
16-Kbyte instruction cachefour-way set-associative, physically addressed; LRU replacement
algorithm
Cache write-back or write-through operation programmable on a per page or per block basis
BPU that performs CR lookahead operations
Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
A 64-entry, two-way set-associative ITLB
A 64-entry, two-way set-associative DTLB
Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
Software table search operations and updates supported through fast trap mechanism
52-bit virtual address; 32-bit physical address
Facilities for enhanced system performance
A 32- or 64-bit split-transaction external data bus with burst transfers
Support for one-level address pipelining and out-of-order bus transactions
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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