參數(shù)資料
型號(hào): MPC8349EZUAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁(yè)數(shù): 49/115頁(yè)
文件大?。?/td> 1228K
代理商: MPC8349EZUAJF
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MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
39
Local Bus
Figure 16 provides the AC test load for the local bus.
Figure 16. Local Bus C Test Load
LALE output fall to LAD output
transition (LATCH hold time)
tLBOTOT2
3—
ns
6
LALE output fall to LAD output
transition (LATCH hold time)
tLBOTOT3
2.5
ns
7
Local bus clock to output valid
tLBKHOV
—3
ns
3
Local bus clock to output high
impedance for LAD/LDP
tLBKHOZ
—4
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of
functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional
block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference
(K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing
(LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going
invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and
LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD
of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output
pin is at least 10pF less than the load on LAD output pins.
6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin
is at least 10pF less than the load on LAD output pins.
7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin
equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be
when the total current delivered through the component pin is less than or equal to the
leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66MHz.
Table 32. Local Bus General Timing Parameters—DLL bypass (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2
RL = 50
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