參數(shù)資料
型號(hào)： MPC8323E-RDB
廠商： Freescale Semiconductor
文件頁數(shù)： 6/82頁
文件大?。?/td> 0K
描述： BOARD REFERENCE DESIGN
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 1
系列： PowerQUICC II™ PRO
類型： MCU
適用于相關(guān)產(chǎn)品： MPC8323E
所含物品： 參考設(shè)計(jì)板、軟件和說明文檔
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
14
Freescale Semiconductor
DDR1 and DDR2 SDRAM
Table 14 provides the recommended operating conditions for the DDR1 SDRAM component(s) of the
MPC8323E when Dn_GVDD(typ) = 2.5 V.
Table 15 provides the DDR1 capacitance Dn_GVDD(typ) = 2.5 V.
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. D
n
_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR1 SDRAM DC Electrical Characteristics for D
n
_GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
D
n
_GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
nREF
0.49
× Dn_GVDD
0.51
× Dn_GVDD
V2
I/O termination voltage
VTT
MVREF
nREF – 0.04
MVREF
nREF + 0.04
V
3
Input high voltage
VIH
MVREF
nREF + 0.15
D
n
_GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF
nREF – 0.15
V
—
Output leakage current
IOZ
–9.9
μA4
Output high current (VOUT = 1.95 V)
IOH
–16.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
16.2
—
mA
—
Notes:
1. D
n
_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
2. MVREF
nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF
nREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
nREF. This rail should track variations in the DC level of MVREFnREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ Dn_GVDD.
Table 15. DDR1 SDRAM Capacitance for D
n
_GVDD(typ) = 2.5 V Interface
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ,DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. D
n
_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V.
Table 13. DDR2 SDRAM Capacitance for D
n
_GVDD(typ) = 1.8 V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8323E-RDB 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway
MPC8323EVRADDC 功能描述:微處理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8323EVRADDCA 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 266MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 266MHZ 516BGA
MPC8323EVRAFDC 功能描述:微處理器 - MPU 8323 NOPB PBGA W/ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8323EVRAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
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