參數(shù)資料
型號(hào): MPC8309CVMAGDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA489
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489
文件頁數(shù): 4/81頁
文件大?。?/td> 484K
代理商: MPC8309CVMAGDCA
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
12
Freescale Semiconductor
Clock Input Timing
The following table shows the estimated typical I/O power dissipation for the device.
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8309.
NOTE
The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This
should be enforced especially on clock signals. Rise time refers to signal
transitions from 10% to 90% of OVDD; fall time refers to transitions from
90% to 10% of OVDD.
4.1
DC Electrical Characteristics
The following table provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC specifications for the
MPC8309. These specifications are also applicable for QE_CLK_IN.
Table 6. Typical I/O Power Dissipation
Interface
Parameter
GVDD
(1.8 V)
OVDD
(3.3 V)
Unit
Comments
DDR I/O
65% utilization
1.8 V
Rs = 20
Rt = 50
1 pair of clocks
266 MHz, 1
16 bits
0.149
—W
Local bus I/O load = 25 pF
1 pair of clocks
66 MHz, 26 bits
—0.415
W
1
QUICC Engine block and other I/Os
TDM serial, HDLC/TRAN serial,
DUART, MII, RMII, Ethernet
management, USB, PCI, SPI, Timer
output, FlexCAN, eSDHC
Note:
1. Typical IO power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
VIH
2.4
OVDD +0.3
V
Input low voltage
VIL
–0.3
0.4
V
SYS_CLK_IN input current
0 V
VIN OVDD
IIN
—±5
A
SYS_CLK_IN input current
0 V
VIN 0.5 V or
OVDD – 0.5 V VIN OVDD
IIN
—±5
A
SYS_CLK_IN input current
0.5 V
VIN OVDD – 0.5 V
IIN
—±50
A
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