參數(shù)資料
型號： MPC8309CVMAGDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA489
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489
文件頁數(shù)： 22/81頁
文件大?。?/td> 484K
代理商： MPC8309CVMAGDCA
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
29
Ethernet and MII Management
8.3.3
IEEE 1588 DC Specifications
The IEEE 1588 DC timing specifications are given in the following table.
8.3.4
IEEE 1588 AC Specifications
The IEEE 1588 AC timing specifications are given in the following table.
Table 26. IEEE 1588 DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
unit
Output high voltage
VOH
IOH = -8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2mA
—0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
- 0.3
0.8
V
Input current
IIN
0V ≤ VIN ≤ OVDD
—± 5
μA
Table 27. IEEE 1588 AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
QE_1588_CLK clock period
tT1588CLK
2.5
—
TRX_CLK 9ns
1, 3
QE_1588_CLK duty cycle
tT1588CLKH/tT1588CLK
40
50
60
%
—
QE_1588_CLK peak-to-peak jitter
tT1588CLKINJ
——
250
ps
—
Rise time QE_1588_CLK
(20%–80%)
tT1588CLKINR
1.0
—
2.0
ns
—
Fall time QE_1588_CLK
(80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
—
QE_1588_CLK_OUT clock period
tT1588CLKOUT
2
tT1588CLK
——
ns
—
QE_1588_CLK_OUT duty cycle
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
—
QE_1588_PULSE_OUT
tT1588OV
0.5
—
3.0
ns
—
QE_1588_TRIG_IN pulse width
tT1588TRIGH
2
tT1588CLK_MAX
——
ns
2
Notes:
1.TRX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8309
PowerQUICC II Pro Integrated Communications Processor Reference Manual,
for a description of TMR_CTRL registers.
2. It needs to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8309 PowerQUICC
II Pro Integrated Communications Processor Reference Manual,
for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100 Mbps modes, the maximum value of tT1588CLK is 3600 and 280ns, respectively.
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