參數(shù)資料
型號(hào): MPC8309CVMAGDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA489
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489
文件頁(yè)數(shù): 21/81頁(yè)
文件大小: 484K
代理商: MPC8309CVMAGDCA
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
28
Freescale Semiconductor
Ethernet and MII Management
The following figure shows the MII management AC timing diagram.
Figure 17. MII Management Interface Timing Diagram
MDC to MDIO delay
tMDKHDX
10
70
ns
MDIO to MDC setup time
tMDDVKH
8.5
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
10
ns
MDC fall time
tMDHF
10
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
Table 25. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 300mV.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
Note
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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