參數(shù)資料
型號(hào)： MPC8241LZQ266B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357
封裝： 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357
文件頁(yè)數(shù)： 6/60頁(yè)
文件大?。?/td> 730K
代理商： MPC8241LZQ266B
14
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.4.3.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in
Section 1.4.3.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths
indicated in Table 4. Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled
number items listed in Table 8.
Table 7. Operating Frequency
Characteristic
166 MHz
200 MHz
266 MHz
Unit
VDD/AVDD/AVDD2 = 1.8 ± 100 mV
Min
Max
Min
Max
Min
Max
Processor frequency
(CPU)
100
166
100
200
100
266
MHz
Memory bus frequency
33
83
33
100
33
133
MHz
PCI input frequency
25–66
MHz
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.6, “PLL Configuration,” for valid
PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1a
Frequency of operation (PCI_SYNC_IN)
25
66
MHz
2, 3
PCI_SYNC_IN rise and fall times
—
2.0
ns
1
4
PCI_SYNC_IN duty cycle measured at 1.4 V
40
60
%
5a
PCI_SYNC_IN pulse width high measured at 1.4 V
6
9
ns
2
5b
PCI_SYNC_IN pulse width low measured at 1.4 V
6
9
ns
2
7
PCI_SYNC_IN jitter
—
200
ps
8a
PCI_CLK[0:4] skew (pin-to-pin)
—
250
ps
8b
SDRAM_CLK[0:3] skew (pin-to-pin)
—
190
ps
3
10
Internal PLL relock time
—
100
s
2, 4, 5
15
DLL lock range with DLL_EXTEND = 0 disabled
(default)
(N
× T
clk – Tdp(max)) ≤ Tloop
≤ (N × T
clk – Tdp(min))
ns
6
16
DLL lock range with DLL_EXTEND = 1 enabled
((N – 0.5)
× T
clk – Tdp(max)) ≤ Tloop
≤ ((N – 0.5) × T
clk – Tdp(min))
ns
6
17
Frequency of operation (OSC_IN)
25
66
MHz
19
OSC_IN rise and fall times
—
5
ns
7
20
OSC_IN duty cycle measured at 1.4 V
40
60
%
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