參數(shù)資料
型號(hào)： MPC8241LZQ266B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357
封裝： 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357
文件頁(yè)數(shù)： 40/60頁(yè)
文件大?。?/td> 730K
代理商： MPC8241LZQ266B
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
45
System Design Information
1.7.3
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active-low inputs should be tied to OVDD. Unused active-high inputs should be connected to
GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD_OVDD, LVDD, and GND pins of
the MPC8241.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8241.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8241. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application notes AN1849/D, MPC107 Design Guide, and
AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information on this topic.
Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).
1.7.4
Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally
be driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the
system to minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120
or less connected to GV
DD_OVDD.
It is recommended that RTC have weak pull-up resistors (2–10 k
) connected to GV
DD_OVDD.
It is recommended that the following signals be pulled up to GVDD_OVDD with weak pull-up resistors
(2–10 k
): SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14,
TRIG_IN/RCS2, QACK/DA0, and DRDY.
It is recommended that the following PCI control signals be pulled up to LVDD (the clamping voltage) with
weak pull-up resistors (2–10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The
resistor values may need to be adjusted stronger to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See
Table 17 for more information.
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND via 1-k
pull-down resistors to ensure a logic zero level is
read into the configuration bits during reset if the default logic-one level is not desired.
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