MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
39
PLL Configuration
1.6
PLL Configuration
The internal PLLs of the MPC8241 are configured by the PLL_CFG[0:4] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory
bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e
CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL
DA[14:15]
B6 D8
Output
GVDD_OVDD
DRV_MEM_CTRL
1, 19
Notes:
1.
Multi-pin signals such as AD[31:0] or MDL[0:31] have their physical package pin numbers listed in order
corresponding to the signal names. Ex: AD0 is on pin U1, AD1 is on pin U2,..., AD31 is on pin U13.
2.
This pin is affected by programmable PCI_HOLD_DEL parameter.
3.
Recommend a weak pull-up resistor (2–10 k
) be placed on this PCI control pin to LV
DD.
4.
GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC8241
is in the reset state.
5.
This pin is a multiplexed signal and appears more than once in this table.
6.
This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up resistor is
not guaranteed, but is sufficient to prevent unused inputs from floating.
7.
This pin is a sustained three-state pin as defined by the PCI Local Bus Specification (Rev. 2.2).
8.
This pin is an open drain signal.
9.
DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC8241 is
in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a
logic 1 is read into configuration bits during reset.
10. This pin has an internal pull-up resistor which is enabled only when the MPC8241 is in the reset state. The value
of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration
bits during reset.
11. This pin is a reset configuration pin.
12. Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to GV
DD_OVDD.
13. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3. 14. External PCI clocking source or fanout buffer may be required for system if using the MPC8241 DUART
functionality since PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
15. OSC_IN utilizes the 3.3-V PCI interface driver which is 5-V tolerant, see
Table 2 for details.
16. This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain.
17. All grounded pins are connected together; connections should not be made to individual pins. The list represents
the balls that are connected to Ground.
18. GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset.
Note that GVDD_OVDD pins are all shorted together, PWRRING. The list represents the balls that are connected
to PWRRING. Connections should not be made to individual PWRRING pins.
19. Treat these pins as No Connects unless using debug address functionality.
20. PLL_CFG signals must be driven on reset.
21. Place a pull-up resistor of 120
or less on the TEST0 pin.
22. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev. 1.1 (A). These signals
use DRV_MEM_CLK for chip Rev. 1.2B.
23. The driver capability of this pin is hardwired to 40
and cannot be changed.
Table 17. MPC8241 Pinout Listing (continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output
Driver Type
Notes