參數(shù)資料
型號： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁數(shù)： 42/58頁
文件大?。?/td> 596K
代理商： MPC8240LZU200X
MPC8240 Integrated Processor Hardware Specications
47
Document Revision History
0.6
Updated Technology in Section 1.3 from 0.32 m to 0.29 m.
Updated Notes in Table 2. Changed line 2 to reect supply voltage wording of the other
lines. Changed notes 2 and 3 to include all LVdd input tolerant signals.
Updated Table 4 eliminating LVdd=5.0V entries for DRV_PCI. Changed LVdd to OVdd
for remaining DRV_PCI entries. Updated notes.
Updated Table 6 to show minimum memory bus operating frequency is 33 MHz.
Updated Table 8 with new characterization data for numbers 22 and 23.
Updated Table 8 adding “/In-line” to “Registered” in Spec 10b2.
Updated Table 9, Table 10, and Table 10 to show changes for MCP and CKE reset
conguration changes for PCI_HOLD_DEL.
Updated Table 12 eliminating 25 MHz column since memory interface does not
operate at this frequency.
Updated Table 17:
- REQ4/DA4 and PLL_CFG[0:4]/DA[10:6] changed Pin Type from Input to I/O.
- DA2, DA[11:13], DA[14:15] changed Pin Type from I/O to Output.
- Reversed vector ordering for the PCI Interface Signals: C/BE[0:3] changed to
C/BE[3:0], AD[0:31] changed to AD[31:0], GNT[0:3] changed to GNT[3:0], and
REQ[0:3] changed to REQ[3:0]. The package pin number orderings were also
reversed meaning that pin functionality did NOT change. For example, AD0 is still on
signal C22, AD1 is still on signal D22, ... AD31 is still on signal V25. This change
was made to make the vectored PCI signals in the MPC8240 Hardware
Specication consistent with the PCI Local Bus Specication and the MPC8240
User Manual vector ordering.
- Deleted Note 19 indicating LAVdd and AVdd are internally connected. Added a
new Note 19 about OSC_IN and EPIC control signals input voltage levels.
Updated Section 1.7.1 eliminating references to LAVdd and AVdd being internally
connected.
Updated Table 24 changing 2K Ohm pull-up resistor on VDD_SENSE to 1K Ohm.
Moved Section 1.7.8 to be at end of JTAG section.
Changed erroneous “C4” reference in Figure 27 title to “TBGA.”
Deleted references to FLOTHERM models in Section 1.7.9.3.
Table 19. Document Revision History (Continued)
Document Revision
Substantive Change(s)
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