參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 4/58頁(yè)
文件大?。?/td> 596K
代理商： MPC8240LZU200X
12
MPC8240 Integrated Processor Hardware Specications
Electrical and Thermal Characteristics
Notes:
1
These specications are for the default driver strengths indicated in Table 4.
2
Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3
Specication value at maximum frequency of operation.
4
Relock time is guaranteed by design and characterization. Relock time is not tested.
5
Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise
and fall times are not tested.
6
Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL
lock after a stable Vdd and PCI_SYNC_IN are reached during the reset sequence. This specication also
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that
HRST_CPU / HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock
time during the reset sequence.
7
DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). Tclk is the period of
one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of
loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. tx0 is a xed delay
inherent in the design when the DLL is at tap point 0 and the DLL is contributing no delay; tx0 equals
approximately 3 ns. See
Figure 5 for DLL locking ranges.
8
Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides
any intentional skew added to the clocking signals from the variable length DLL synchronization feedback
loop, i.e. the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal
after the DLL is locked. While pin to pin skew between SDRAM_CLKs can be measured, the relationship
between the internal sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is
guaranteed by design.
Figure 4 shows the PCI_SYNC_IN input clock timing diagram, and Figure 5 shows the DLL locking range
loop delay versus frequency of operation.
15
DLL lock range with DLL_EXTEND = 0 disabled (default)
0
≤ (NTclk - tloop - tx0) ≤ 7ns
7
16
DLL lock range with DLL_EXTEND = 1 enabled
0 ≤ (NTclk - Tclk/2 - tloop -
tx0) ≤ 7
ns
7
17
Frequency of operation (OSC_IN)
25
66
MHz
18
OSC_IN cycle time
40
15
ns
19
OSC_IN rise and fall times
—
5
ns
5
20
OSC_IN duty cycle measured at 1.4 V
40
60
%
21
OSC_IN frequency stability
—
100
ppm
22
OSC_IN VIH (loaded)
2.0
V
23
OSC_IN VIL (loaded)
0.8
V
Table 7. Clock AC Timing Specifications (Continued)
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V
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