參數(shù)資料
型號(hào): MPC8240LZU200X
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù): 34/58頁(yè)
文件大?。?/td> 596K
代理商: MPC8240LZU200X
4
MPC8240 Integrated Processor Hardware Specications
Features
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (ve request/grant pairs)
— PCI agent mode capability
– Address translation unit
– Internal conguration registers accessible from PCI
— Two-channel integrated DMA controller
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering: read or write discontinuous memory
– 64-byte transfer queue
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– PCI-to-local memory
– Local-to-PCI memory
— Message unit
–I2O message controller
– Two door-bell registers
– Inbound and outbound messaging registers
—I2C controller with full master/slave support
— Embedded programmable interrupt controller (EPIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers
— Integrated PCI bus and SDRAM clock generation
— Programmable memory and PCI bus output drivers
— Debug features
– Watchpoint monitor
– Address attribute and PCI attribute signals
– JTAG/COP: common on-board processor for in-circuit hardware debugging
– Performance monitor
603e core
— High-performance, superscalar 603e core
— Integer unit (IU), oating-point unit (FPU) (user enabled or disabled), load/store unit (LSU),
system register unit (SRU), and a branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—entire cache or on a per-way basis up to 3 of 4 ways.
— Dynamic power management
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