External Signals
MOTOROLA
MPC823 USER’S MANUAL
2-7
EXTERNAL
SIGNALS
2
TEXP
D5
Timer Expired—This output signal reflects the status of the TEXPS bit of the
PLPRCR register in the clock interface.
WAIT_B
C4
Wait Slot B—This input signal, if asserted low, causes the completion of a
transaction to be delayed on the PCMCIA-controlled Slot B.
ALE_B
DSCK
AT1
B8
Address Latch Enable B—This output signal is asserted when the MPC823
initiates an access to a region under the control of the PCMCIA socket B interface.
Development Serial Clock—This input signal is the clock for the debug port
interface.
Address Type 1—This bidirectional three-state signal is driven by the MPC823
when it initiates a transaction on the external bus. When the transaction is initiated
by the internal core, it indicates if the transfer is for problem or privilege state.
IP_B0
IWP0
VFLS0
A8
Input Port B 0—This input signal is sensed by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Instruction Watchpoint 0—This output signal reports the detection of an instruction
watchpoint in the program flow executed by the internal core.
Visible History Buffer Flushes Status—This output signal is output by the MPC823
when you need program instructions flow tracking. It reports the number of
instructions flushed from the history buffer in the internal core.
IP_B1
IWP1
VFLS1
C8
Input Port B 1—This input signal is sensed by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Instruction Watchpoint 1—This output signal reports the detection of an instruction
watchpoint in the program flow executed by the internal core.
Visible History Buffer Flushes Status—This output signal is output by the MPC823
when you need program instructions flow tracking. It reports the number of
instructions flushed from the history buffer in the internal core.
IP_B2
IOIS16_B
AT2
D7
Input Port B 2—This input signal is sensed by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
I/O Device B is 16 Bits Port Size—This input signal is monitored by the MPC823
when a PCMCIA interface transaction is initiated to an I/O region in socket B within
the PCMCIA space.
Address Type 2—This bidirectional three-state signal is driven by the MPC823
when it initiates a transaction on the external bus. When the transaction is initiated
by the internal core, it indicates if the transfer is instruction or data.
IP_B3
IWP2
VF2
A9
Input Port B 3—This input signal is monitored by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Instruction Watchpoint 2—This output signal reports the detection of an instruction
watchpoint in the program flow executed by the internal core.
Visible Instruction Queue Flush Status—This output signal, together with VF0 and
VF1, is output by the MPC823 when you need program instruction flow tracking. VFx
reports the number of instructions flushed from the instruction queue in the internal
core.
IP_B4
LWP0
VF0
B9
Input Port B 4—This input signal is monitored by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Load/Store Watchpoint 0—This output signal reports the detection of a data
watchpoint in the program flow executed by the internal core.
Visible Instruction Queue Flushes Status—This output signal, together with VF1
and VF2, is output by the MPC823 when you need program instructions flow
tracking. VF reports the number of instructions flushed from the instruction queue in
the internal core.
IP_B5
LWP1
VF1
C9
Input Port B 5—This input signal is monitored by the MPC823 and its value and
changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Load/Store Watchpoint 1—This output signal reports the detection of a data
watchpoint in the program flow executed by the internal core.
Visible Instruction Queue Flushes Status—This output signal, together with VF0
and VF2, is output by the MPC823 when you need program instructions flow
tracking. VF reports the number of instructions flushed from the instruction queue in
the internal core.
Table 2-1. Signal Descriptions (Continued)
SIGNAL
PIN NUMBER
DESCRIPTION