Communication Processor Module
16-146
MPC823 USER’S MANUAL
MOTOROLA
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
The M channel is used to transfer data between layer 1 devices and the control unit (the
core) and the C/I channel is used to control activation/deactivation procedures or to switch
test loops by the control unit. The M and C/I channels of the GCI bus should be routed to
SMC1 or SMC2, which have modes to support the channel protocols. The MPC823 can
support any channel of the GCI bus in the primary rate by modifying the serial interface RAM
programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation
since it can access each bit of the GCI separately. The current-route RAM specifies which
the bits that are supported by the interface and serial controller. The receiver only receives
the bits that are enabled by the serial interface RAM and the transmitter only transmits the
bits that are enabled by the serial interface RAM and does not drive L1TXDA. Otherwise,
L1TXDA is an open-drain output and should be externally pulled high.
The MPC823 supports contention detection on the D channel of the SCIT bus. When the
MPC823 has data to transmit on the D channel, it checks a SCIT bus bit that is marked with
a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the
physical layer bus for activity on the D channel and indicates on this bit that the channel is
free. If a collision is detected on the D channel, the physical layer device sets bit 4 of C/I
channel 2 to logic high. The MPC823 then aborts its transmission and retransmits the frame
when this bit is set again. This procedure is automatically handled for the first two buffers of
a frame.
16.7.7.1 GCI ACTIVATION/DEACTIVATION PROCEDURE. In the deactivated state, the
clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the
MPC823 by enabling the clock pulses and sending an indication to C/I channel 0. Using a
maskable interrupt, the MPC823 lets the core know that a valid indication has been received
in the SMC receive buffer descriptor.
When the core activates the line, the data output of L1TXDA is programmed to zero by
setting the STZA bit in the SIMODE register. Code 0 (command timing TIM) is transmitted
on C/I channel 0 to the layer 1 device until the STZA bit is reset. The physical layer device
resumes the clock pulses and gives an indication in C/I channel 0. The core should reset the
STZA bit to enable data output.
16.7.7.2 PROGRAMMING THE GCI INTERFACE. There are two modes of the GCI
interface—normal and SCIT.
16.7.7.2.1 Normal Mode. You can program and configure the channels used for the GCI
bus interface. First, program the SIMODE register to the GCI/SCIT mode for that channel.
This mode defines the sync pulse to GCI sync for framing and data clock as one-half the
input clock rate. You can program more than one channel to interface to the GCI bus. Also,
if the receive and transmit section are used for interfacing the same GCI bus, using the
CRTA bit you should internally connect the receive clock and sync signals to the serial
interface RAM transmit section. Then you should define the GCI frame routing and strobe
select using the serial interface RAM.