參數(shù)資料
型號(hào): MPC755BPX300LX
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA360
封裝: 25 X 25 MM, 2.77 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-360
文件頁(yè)數(shù): 3/48頁(yè)
文件大?。?/td> 1265K
代理商: MPC755BPX300LX
MPC755 RISC Microprocessor Hardware Specifications
11
Electrical and Thermal Characteristics
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold
by maximum processor core frequency; see Section 1.10, “Ordering Information”.
1.4.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
Maximum
430
mW
1, 2
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O Supply Power
(OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system
dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mW and L2AVdd
=15 mW.
2. Maximum power is measured at 105°C and Vdd = 2.0 V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units maximally busy.
3. Typical power is an average value measured at 65°C and Vdd = 2.0 V in a system executing typical applications
and benchmark sequences.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
200
300
200
350
200
400
MHz
1
VCO frequency
fVCO
400
600
400
700
400
800
MHz
1
SYSCLK frequency
fSYSCLK
25
100
25
100
25
100
MHz
1
SYSCLK cycle time
tSYSCLK
10
40
10
40
10
40
ns
SYSCLK rise and fall time
tKR & tKF
—2.0
ns
2
tKR & tKF
—1.0
ns
2
SYSCLK duty cycle measured
at OVdd/2
tKHKL/
tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
±150
±150
±150
ps
3, 4
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
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