參數(shù)資料
型號: MPC755BPX300LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA360
封裝: 25 X 25 MM, 2.77 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-360
文件頁數(shù): 13/48頁
文件大小: 1265K
代理商: MPC755BPX300LX
20
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC755.
Figure 11. AC Test Load for the JTAG Interface
Figure 12 provides the JTAG clock input timing diagram.
Figure 12. JTAG Clock Input Timing Diagram
Figure 13 provides the TRST timing diagram.
Valid Times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
ns
4
Output Hold Times:
Boundary-scan data
TDO
tJLDH
tJLOH
25
12
ns
4
TCK to Output High Impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4,5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-ohm load
(See Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)1 (Continued)
At recommended operating conditions (See Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
OUTPUT
Z0 = 50
OVdd/2
RL = 50
TCLK
VM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR
tJF
tJHJL
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