參數(shù)資料
型號(hào)： MPC603EFEX266LX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, CQFP240
封裝： 32 X 32 MM, 0.50 MM PITCH, CERAMIC, QFP-240
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 498K
代理商： MPC603EFEX266LX
8
PID6-603e Hardware Specifications, Rev 2
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
1.4.2.2 Input AC Specications
Table 7 provides the input AC timing specications for the 603e as dened in Figure 2 and Figure 3.
Table 7. Input AC Timing Specifications
At recommended operating conditions. See Table 2.
Num
Characteristic
100 MHz
133.33 MHz
Unit
Notes
Min
Max
Min
Max
10a
Address/data/transfer attribute inputs valid to SYSCLK
(input setup)
3.0
—
3.0
—
ns
2
10b
All other inputs valid to SYSCLK (input setup)
5.0
—
5.0
—
ns
3
10c
Mode select inputs valid to HRESET (input setup) (for
DRTRY, QACK and TLBISYNC)
8*tsysclk
—
8*tsysclk
—
ns
4,5,6,
7
11a
SYSCLK to address/data/transfer attribute inputs
invalid (input hold)
1.0
—
1.0
—
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
—
1.0
—
ns
3
11c
HRESET to mode select inputs invalid (input hold) (for
DRTRY, QACK, and TLBISYNC)
0
—
0
—
ns
4,6,7
Notes:
1. All input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V
of the rising edge of the input SYSCLK (see Figure 2). Both input and output timings are measured at the
pin.
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],
TC[0–1], TBST, TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following— TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode select only. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
VM
CVil
CVih
SYSCLK
VM = Midpoint Voltage (1.4 V)
2
3
1
44
VM
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For More Information On This Product,
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