MOTOROLA
Chapter 6. System Configuration and Protection
6-7
External Master Modes
accesses is less than four clocks. The external master access and retry timings are described
The external master may access the internal MPC565/MPC566 special registers that are
located outside the RCPU. In order to access one of these MPC565/MPC566 registers,
program the EMCR to MPC565/MPC566 special register access (CONT = 1 and SUPU = 0
in EMCR). Next, access the register by providing the address according to the
MPC565/MPC566 address map. Only the first external master access that follows EMCR
setting will be assigned to the special register map; any subsequent accesses will be directed
to the normal address map. This is done in order to enable access to the EMCR again after
the required MPC565/MPC566 special register access.
Peripheral mode does not require external bus arbitration between the external master and
the internal RCPU, since the internal RCPU is disabled. The BR and BB signals should be
connected to ground, and the internal bus arbitration should be selected in order to prevent
the “slave” MPC565/MPC566 from occupying the external bus. Internal bus arbitration is
6.2.2
Address Decoding for External Accesses
During an external master access, the USIU compares the external address with the internal
address block to determine if MPC565/MPC566 operation is required. Since only 24 of the
32 internal address bits are available on the external bus, the USIU assigns zeros to the most
significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
Normal external access. If the CONT bit in EMCR is cleared, the address is compared to
MPC565/MPC566 special register external access. If the CONT bit in EMCR is set
by the previous external master access, the address is compared to the
Memory controller external access. If the first two comparisons do not match, the
internal memory controller determines whether the address matches an address
assigned to one of the regions. If it finds a match, the memory controller generates
the appropriate chip select and attribute accordingly
When trying to fetch an MPC565/MPC566 special register from an external master, the
address might be aliased to one of the external devices on the external bus. If this device is
selected by the MPC565/MPC566 internal memory controller, this aliasing does not occur
since the chip select is disabled. If the device has its own address decoding or is being
selected by external logic, this case is resolved.