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參數(shù)資料
| 型號： | MPC555 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MPC555 |
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Application Note
AN1778
22
MOTOROLA
The last four bits of this register are the clock prescaler, as shown in
Table 6
.
Set up the MDASM to count on rising edges (bits 3:4) and to use the
MMCSM clock. The clock prescaler is governed by the same values as
the PWM prescaler bits listed in
Table 4
in the PWM section. Set it up to
follow the MMCSM clock with a prescaler division of 1. This means that
the counter will run at 10 MHz or 100 ns per count.
Type this line to set up the MDASM counter:
write -w 0x306036 = 0x0eff
To ensure that the counter starts properly, reset it. To reset the counter,
load all 0s into the modulus latch register. This is a read/write register
containing the 16-bit value of the counter used by the MDASM.
Type this line to reset the MDASM counter:
write -w 0x306032 = 0x0000
With the clock now running, the MDASM can be set up to detect the
waveform periods and reference them to this counter.
Table 6. MMCSMSCR Bit Settings
Bit(s)
0
Name
PINC
Description
Clock input pin status. This read-only status bit reflects the logic state of the clock input pin.
Modulus load input pin status. This read-only status bit reflects the logic state of the
modulus load pin.
Freeze enable. This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
Modulus load falling edge/rising edge sensitivity. These active high read/write control bits
set falling edge and rising edge sensitivity, respectively.
00 = Disabled
01 = MMCSMCNT load on rising edges
10 = MMCSMCNT load on falling edges
11 = MMCSMCNT load on rising and falling edges
Clock select. These read/write control bits select the clock source for the modulus counter.
00 = Disabled
01 = Falling edge of pin
10 = Rising edge of pin
11 = MMCSM clock prescaler
—
Clock prescaler. This 8-bit read/write data register stores the twos complement of the
desired modulus value for loading into the built-in 8-bit clock prescaler. The new value is
loaded into the prescaler counter when the next counter overflow occurs or when the CLS
bits are set to select the clock prescaler as the clock source.
Table 4
gives the clock divide
ratio according to the CP values
1
PINL
2
FREN
3:4
EDGN,
EDGP
5:6
CLS
7
—
8:15
CP
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