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參數(shù)資料
| 型號： | MPC555 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 219K |
| 代理商： | MPC555 |
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Application Note
AN1778
16
MOTOROLA
Following the register description and the information in
Table 2
, set
bit 1 high to enable the counter and write 0010 to bits 12 to 15 to set the
divider to 2 for the fastest counter possible. The faster the counter, the
faster the waveforms that can be produced. All other bits should be 0.
Converting these binary bits to hex (use
Decimal to Binary to
Hexadecimal Conversion Table
, if necessary), 0x8002 must be written
to register 0x306816 (MCPSMCR).
Type this line into the SDS command window:
write -w 0x306816 = 0x8002
Next, the individual PWM channels must be programmed.
PWM Period
Register
(MPWMSMPERR)
The MPWMSMPERR sets the number of divisions per period of the
waveform, for example, resolution of a single period.
Special consideration must be taken when choosing the resolution of the
wave to be produced because it involves a compromise. The resolution
of the wave is inversely proportional to the maximum frequency that can
be produced. Higher resolution requires more cycles of the reference
clock per period and, therefore, a lower overall frequency. (See
PWM
ReferenceClock
.)Thecontentsoftheperiodregistercontainthebinary
value corresponding to the number of MIOS clocks allocated to the
period of the waveform.
PWM channels 0 and 2 will be programmed with the same period
resolution:
Type this line for channel 0:
write -w 0x306000 = 0x0002
And the following for channel 2:
write -w 0x306010 = 0x0002
PWM Pulse
Register
(MPWMSMPULR)
This register sets the number (in binary) of divisions from
PWM Period
Register (MPWMSMPERR)
that are high. This means that the ratio of
the pulse register to the period register determines the duty cycle of the
produced signal. The value in the pulse register must be less than the
value contained in the period register.
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