參數(shù)資料
型號(hào): MPC555
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁(yè)數(shù): 14/32頁(yè)
文件大?。?/td> 219K
代理商: MPC555
Application Note
AN1778
14
MOTOROLA
Figure 4. PWM Clock Arrangement
Theeight pulse widthmodulators are part ofthe MIOS submodule on the
MPC555. To use the PWM channels, the MIOS counter must be started.
Normally, the IMB (intermodule bus) clock is half the system clock, but
for this example it has to be set to full speed at 20 MHz in the initialization
script. This was done to maintain consistency if the system clock is set
to 40 MHz with a default half speed bus of 20 MHz. The IMB can be set
to 20 MHz whether the MPC555 is operating at 20 or 40 MHz.
The MIOS counter prescaler submodule (MCPSM) divides the system
IMB clock (20 MHz for this note) to generate the counter clock. It is
designed to provide all the submodules with the same division of the
main clock. The clock signal is prescaled by loading the value of the
clock prescaler register into the prescaler counter every time it
overflows. This allows all prescaling factors between 2 and 16. Counting
is enabled by asserting the PREN bit in the control register.
NOTE:
Because the PWM uses the MIOS counter to time itself, the maximum
frequency that the PWM can generate is half of the MIOS counter clock,
even if the PWM channel divider is set to 1. This is because the PWM
uses 1 count of the MIOS counter per transition of the PWM signal.
The IMB bus speed register was programmed to full speed in the
initialization of the MPC555. (If the MPC555 is running at 40 MHz,
20 MHZ DEFAULT
(USIU)
(F
SYS
)
INTERMODULE BUS
SET IMB CLOCK =
HSPEED =
20 MHZ
SYS CLOCK
MIOS COUNTER CLK
DIVIDER (2 TO 16)
10 MHZ
(MCPSM)
PWM CHANNEL
DIVIDER (1 TO 256)
(MAX IS 1/2 OF
MIOS COUNTER —
2 COUNTS/PERIOD)
(DEFAULT = 1/2 F
SYS
)
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