參數(shù)資料
型號(hào)： MPC106ARX83TG
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 451K
代理商： MPC106ARX83TG
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
7
80C1000_MA002_02
Features
The Tsi106 provides a PowerPC microprocessor CHRP-compliant bridge between the PowerPC
microprocessor family and the PCI bus. CHRP documentation provides a set of specifications that define a
unified personal computer architecture. PCI support allows the rapid design of systems using peripherals
already designed for PCI and the other standard interfaces available in the personal computer hardware
environment. The Tsi106 integrates secondary cache control and a high-performance memory controller,
uses an advanced, 3.3-V CMOS process technology, and is fully compatible with TTL devices.
The Tsi106 supports a programmable interface to a variety of PowerPC microprocessors operating at select
bus speeds. The 60x address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor
interface of the Tsi106 uses a subset of the 60x bus protocol, supporting single-beat and burst data
transfers. The address and data buses are decoupled to support pipelined transactions.
The Tsi106 provides support for the following configurations of 60x processors and L2 cache:
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache
controller of the Tsi106
Up to four 60x processors plus an externally controlled L2 cache (such as the Motorola MPC2605
integrated secondary cache)
The memory interface controls processor and PCI interactions to main memory and is capable of
supporting a variety of configurations using DRAM, EDO, SDRAM, ROM, or Flash ROM.
The PCI interface of the Tsi106 complies with the PCI Local Bus Specification, Revision 2.1, and follows
the guidelines in the PCI System Design Guide, Revision 1.0, for host bridge architecture. The PCI
interface connects the processor and memory buses to the PCI bus, to which I/O components are
connected. The PCI bus uses a 32-bit multiplexed address/data bus, plus various control and error signals.
The PCI interface of the Tsi106 functions as both a master and target device. As a master, the Tsi106
supports read and write operations to the PCI memory space, the PCI I/O space, and the PCI configuration
space. The Tsi106 also supports PCI special-cycle and interrupt-acknowledge commands. As a target, the
Tsi106 supports read and write operations to system memory.
The Tsi106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend.
The design of the Tsi106 is fully static, allowing internal logic states to be preserved during all
power-saving modes.
1.2 Features
This section summarizes the major features of the Tsi106, as follows:
60x processor interface
— Supports up to four 60x processors
— Supports various operating frequencies and bus divider ratios
— 32-bit address bus, 64-bit data bus
— Supports full memory coherency
— Supports optional 60x local bus slave
— Decoupled address and data buses for pipelining of 60x accesses
— Store gathering on 60x-to-PCI writes
相關(guān)PDF資料
PDF描述
MPC106ARX83DG PCI BUS CONTROLLER, CBGA304
MPC106ARX66CG PCI BUS CONTROLLER, CBGA304
MPC5200BV400 400 MHz, MICROPROCESSOR, PBGA272
MPC5200CBV266R2 266 MHz, MICROPROCESSOR, PBGA272
MPC5200CBV266BR2 266 MHz, MICROPROCESSOR, PBGA272
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