參數(shù)資料
型號(hào)： MPC106ARX83TG
元件分類(lèi)： 總線(xiàn)控制器
英文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁(yè)數(shù)： 29/32頁(yè)
文件大小： 451K
代理商： MPC106ARX83TG
6
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
80C1000_MA002_02
Overview
In this document, the term ‘60x’ is used to denote a 32-bit microprocessor from the PowerPC architecture
family that conforms to the bus interface of the PowerPC 601, PowerPC 603, or PowerPC 604
microprocessors. Note that this does not include the PowerPC 602 microprocessor which has a
multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is specified for
32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32
bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision).
1.1 Overview
The Tsi106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between
a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus, and
main memory. This section provides a block diagram showing the major functional units of the Tsi106 and
describes briefly how those units interact.
Figure 1 shows the major functional units within the Tsi106. Note that this is a conceptual block diagram
intended to show the basic features rather than how these features are physically implemented on the
device.
Figure 1. Block Diagram
32-bit Address and Data
25-33 MHz PCI Bus (Rev. 2.1)
64-bit Data/32-bit Address
66-83 MHz Bus
66 MHz,
64-bit Bus
DRAM,
SDRAM,
ROM,
Flash
Up to 1-Mbyte
of SRAM
80C1000_BK001_01
IEEE1149.1
Boundary
Scan
Processor Interface
PCI Interface
JTAG
Memor
y
Interf
ace
L2 Cache
Interface
Power
Management
Error/Interrupt
Control
Configuration
Registers
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