參數(shù)資料
型號: MPC106ARX83DG
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, CBGA304
封裝: 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁數(shù): 15/32頁
文件大?。?/td> 451K
代理商: MPC106ARX83DG
22
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
80C1000_MA002_02
Pinout Listings
CKE/DBGLB
J10
High
Output
FOE
D13
Low
Output
MA0/SDBA1/SDMA0/AR0 N15
High
Output
SDMA1
(XATS)
P1
High
Output
MA1/SDBA0/AR9
U16
High
Output
MA[2–12]/SDMA[2–12]/AR
[10–20]
T16, R16, P15, P16, N16, M15, M16, L15, K15, K16, J16
High
Output
MDLE/SDCAS
E13
Low
Output
PAR[0–7]/AR[1–8]
D16, D15, C16, C15, B16, C14, A16, B15
High
I/O
PPEN
J14
Low
Output
RAS/CS[0–7]
M14, L13, K13, K14, K12, L10, J12, K11
Low
Output
RCS0
R15
Low
I/O
RCS1
J13
Low
Output
RTC
G15
High
Input
SDRAS
(PIRQ)
H10
Low
Output
WE
T15
Low
Output
PCI Interface Signals1
AD[31–0]
A4, C13, B5, D12, A5, C12, B6, D11, C11, B7, D10, A7, C10, B8,
D9, A8, B10, D8, A11, C7, B11, D7, A12, C6, B12, C5, A13, D5,
A14, C4, B14, D4
High
I/O
C/BE[3–0]
A6, C9, C8, D6
Low
I/O
DEVSEL
F8
Low
I/O
FLSHREQ
A3
Low
Input
FRAME
A10
Low
I/O
GNT
A15
Low
Input
IRDY
E8
Low
I/O
ISA_MASTER
(BERR)
B3
Low
Input
LOCK
G8
Low
Input
MEMACK
A2
Low
Output
PAR
G9
High
I/O
PERR
F9
Low
I/O
PIRQ
(SDRAS)
H10
Low
Output
REQ
B4
Low
Output
SERR
E9
Low
I/O
Table 10. Pinout Listing (Continued)
Signal Name
Pin Number
Active
I/O
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