參數(shù)資料
型號: MPC106ARX83DG
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, CBGA304
封裝: 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁數(shù): 13/32頁
文件大小: 451K
代理商: MPC106ARX83DG
20
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
80C1000_MA002_02
Pinout Listings
1.6 Pinout Listings
Table 10 provides the pinout listing for the Tsi106. Some signals have dual functions and are shown more
than once.
Table 10. Pinout Listing
Signal Name
Pin Number
Active
I/O
60x Processor Interface Signals
A[0–31]
R2, P2, N2, M2, L2, K2, J5, K4, K5, K6, J2, J6, J3, J4, H3, H4, H2,
G2, F1, E1, E2, F4, E3, D1, C1, C2, B1, C3, B2, E4, D3, E5
High
I/O
AACK
D2
Low
I/O
ARTRY
F2
Low
I/O
BG0
K3
Low
Output
BG1
(DIRTY_OUT)
R4
Low
Output
BG2
(TWE)
R5
Low
Output
BG3
(DCS)
T1
Low
Output
BR0
L3
Low
Input
BR1
(DIRTY_IN)
T3
Low
Input
BR2
(TV)
T6
Low
Input
BR3
(BA0)
T5
Low
Input
CI
N3
Low
I/O
DBG0
L5
Low
Output
DBG1
(TOE)
U4
Low
Output
DBG2
(DWE0)
P3
Low
Output
DBG3
(DWE1)
H11
Low
Output
DBGLB
(CKE)
J10
Low
Output
DH[0–31]
T14, R13, R14, P13, P14, N13, U3, W1, V2, W2, V3, W3, V4, W4,
V5, W5, V6, W6, V7, W7, V8, W8, N8, W9, V9, W10, V10, W11,
V11, W12, V12, W13
High
I/O
DL[0–31]
U6, T7, U7, T8, U8, R8, P8, N9, P9, R9, U9, T9, U10, T10, U13,
T13, R12, N14, M13, T2, U1, U2, V1, U15, V16, U14, W16, V15,
W15, V14, W14, V13
High
I/O
GBL
M3
Low
I/O
LBCLAIM
N4
Low
Input
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