參數(shù)資料
型號(hào)： ML9620GAZ210
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù)： 52/79頁(yè)
文件大?。?/td> 449K
代理商： ML9620GAZ210
ML9620 User’s Manual
Chapter 3
Operational Description
3 - 16
3.11.4 Loop Back combined with Silent mode
It is also possible to combine Loop Back mode and Silent mode by
programming bits Lback and Silent to ‘1’at the same time.
This mode
can be used for a ‘Hot Selftest’, meaning the ML9620 can be tested without
affecting a running CAN system connected to the pins TX and RX.
In
this mode the RX pin is disconnected from the CAN Control and the TX
pin is held recessive.
Figure 3-10 shows the connection of signals TX
and RX to the CAN Control in case of the combination of Loop Back mode
with Silent mode.
Figure 3-10
CAN Control in Loop Back combined with Silent mode
3.11.5 Basic mode
The CAN Control can be set in Basic mode by programming the CAN Optional Register bit Basic to ‘1’.
In this
mode the ML9620 module runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer.
The transmission of the contents of the IF1 Registers is requested
by writing the Busy bit of the IF1 Command Request Register to ‘1’.
The IF1 Registers are locked while the
Busy bit is set.
The Busy bit indicates that the transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN Control and the
transmission is started.
When the transmission has completed, the Busy bit is reset and the locked IF1 Registers
are released.
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request Register
while the IF1 Registers are locked.
If the MCU has reset the Busy bit, a possible retransmission in case of lost
arbitration or in case of an error is disabled.
The IF2 Registers are used as Receive Buffer.
After the reception of a message the contents of the RX/TX shift
register (=received lastest message) is stored into the IF2 Registers, without any acceptance filtering.
Additionally, the actual contents of the shift register can be monitored during the message transfer.
Each time a
read Message Object is initiated by writing the Busy bit of the IF2 Command Request Register to ‘1’, the contents
of the shift register is stored into the IF2 Registers.
In Basic mode the evaluation of all Message Object related control and status bits and of the control bits of the
IFm Command Mask Registers is turned off.
The message number of the Command request registers is not
evaluated.
The NewDat and MsgLst bits of the IF2 Message Control Register retain their function, DLC[3:0]
will show the received DLC, the other control bits will be read as ‘0’.
In Basic mode the ready output
PRDY/SWAIT is disabled (always HIGH level).
3.11.6 Software control of Pin TX
Four output functions are available for the CAN transmit pin TX.
Additionally to its default function – the serial
data output – it can drive the CAN Sample Point signal (Folling edge after “1”(=high) output of fosc/2 time) to
monitor CAN Control’s bit timing and it can drive constant dominant or recessive values.
The last two functions,
combined with the readable CAN receive pin RX, can be used to check the CAN bus’ physical layer.
The output mode of pin TX is selected by programming the CAN Optional Register bits Tx[1:0] as described in
chapter 2.2.9.
The three test functions for pin TX interfere with all CAN protocol functions.
TX must be left in its default
function when CAN message transfer or any of the test modes Loop Back mode, Silent mode, or Basic mode are
selected.
ML9620
CAN Control
TX
RX
TX
RX
=1
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