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| 型號： | ML9620GAZ210 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 44/79頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ML9620GAZ210 |
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ML9620 User’s Manual
Chapter 3
Operational Description
3 - 9
3.8
Configuration of a FIFO Buffer
With the exception of the EoB bit, the configuration of Receive Objects belonging to a FIFO Buffer is the same as
the configuration of a (single) Receive Object, see section 3.6.
To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and masks (if used) of these
Message Objects have to be programmed to matching values.
Due to the implicit priority of the Message Objects,
the Message Object with the lowest number will be the first Message Object of the FIFO Buffer.
The EoB bit of
all Message Objects of a FIFO Buffer except the last have to be programmed to ‘0’.
The EoB bits of the last
Message Object of a FIFO Buffer is set to ‘1’, configuring it as the End of the Block.
3.8.1 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO Buffer are stored into a Message Object of this FIFO
Buffer starting with the Message Object with the lowest message number.
When a message is stored into a Message Object of a FIFO Buffer the NewDat bit of this Message Object is set.
By setting NewDat while EoB is ‘0’ the Message Object is locked for further write accesses by the Message
Handler until the MCU has written the NewDat bit back to ‘0’.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached.
If none of
the preceding Message Objects is released by writing NewDat to ‘0’, all further messages for this FIFO Buffer
will be written into the last Message Object of the FIFO Buffer and therefore overwrite previous messages.
3.8.2
Reading from a FIFO Buffer
When the MCU transfers the contents of Message Object to the IFm Message Bugger registers by writing its
number to the IFm Command Request Register, the corresponding Command Mask Register should be
programmed the way that bits NewDat and IntPnd are reset to ‘0’ (TxRqst/NewDat = ‘1’ and ClrIntPnd = ‘1’).
The values of these bits in the Message Control Register always reflect the status before resetting the bits.
To assure the correct function of a FIFO Buffer, the MCU should read out the Message Objects starting at the
FIFO Object with the lowest message number.
Figure 3-5 shows how a set of Message Objects which are concatenated to a FIFO Buffer can be handled by the
MCU.
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