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參數(shù)資料
| 型號(hào)： | ML9620GAZ210 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 20/79頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ML9620GAZ210 |
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ML9620 User’s Manual
Chapter 2
Register Descriptions
2 – 10
2.3
Message Interface Register Sets
There are two sets of Interface Registers, which are used to control the MCU access to the Message RAM.
The
Interface Registers avoid conflicts between MCU accesses to the Message RAM and CAN message reception
and transmission by buffering the data to be transferred.
A complete Message Object (see chapter 2.3.5) or
parts of the Message Object may be transferred between the Message RAM and the IFm Message Buffer
registers (see chapter 2.3.4) in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic).
They can be used the
way that one set of registers is used for data transfer to the Message RAM while the other set of registers is used
for the data transfer from the Message RAM, allowing both processes to be interrupted by each other.
Table
2-1 gives an overview of the two Interface Register sets.
Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers.
The Command Mask Register specifies the direction of the data transfer and which parts of a Message Object
will be transferred. The Command Request Register is used to select a Message Object in the Message RAM as
target or source for the transfer and to start the action specified in the Command Mask Register.
Table 2-1 IF1 and IF2 Message Interface Register Sets
Address
IF1 Register Sets
Address
IF2 Register Sets
CAN Base + 0x10
IF1 Command Request register
CAN Base + 0x40
IF2 Command Request register
CAN Base + 0x11
IF1 Busy register
CAN Base + 0x41
IF2 Busy register
CAN Base + 0x12
IF1 Command Mask register
CAN Base + 0x42
IF2 Command Mask register
CAN Base + 0x13
reserved
CAN Base + 0x43
reserved
CAN Base + 0x14
IF1 Mask 1 register
CAN Base + 0x44
IF2 Mask 1 register
CAN Base + 0x15
IF1 Mask 2 register
CAN Base + 0x45
IF2 Mask 2 register
CAN Base + 0x16
IF1 Mask 3 register
CAN Base + 0x46
IF2 Mask 3 register
CAN Base + 0x17
IF1 Mask 4 register
CAN Base + 0x47
IF2 Mask 4 register
CAN Base + 0x18
IF1 Identifier 1 register
CAN Base + 0x48
IF2 Identifier 1 register
CAN Base + 0x19
IF1 Identifier 2 register
CAN Base + 0x49
IF2 Identifier 2 register
CAN Base + 0x1A
IF1 Identifier 3 register
CAN Base + 0x4A
IF2 Identifier 3 register
CAN Base + 0x1B
IF1 Identifier 4 register
CAN Base + 0x4B
IF2 Identifier 4 register
CAN Base + 0x1C
IF1 Message Control 1 register
CAN Base + 0x4C
IF2 Message Control 1 register
CAN Base + 0x1D
IF1 Message Control 2 register
CAN Base + 0x4D
IF2 Message Control 2 register
CAN Base + 0x1E
IF1 Data A1 register
CAN Base + 0x4E
IF2 Data A1 register
CAN Base + 0x1F
IF1 Data A2 register
CAN Base + 0x4F
IF2 Data A2 register
CAN Base + 0x20
IF1 Data A3 register
CAN Base + 0x50
IF2 Data A3 register
CAN Base + 0x21
IF1 Data A4 register
CAN Base + 0x51
IF2 Data A4 register
CAN Base + 0x22
IF1 Data B1 register
CAN Base + 0x52
IF2 Data B1 register
CAN Base + 0x23
IF1 Data B2 register
CAN Base + 0x53
IF2 Data B2 register
CAN Base + 0x24
IF1 Data B3 register
CAN Base + 0x54
IF2 Data B3 register
CAN Base + 0x25
IF1 Data B4 register
CAN Base + 0x55
IF2 Data B4 register
Note
Reserved bits return '0' for reads and should be written '0' to them.
Operation is not guaranteed for a writing
'1' to them.
As exeption, reserved bits in IF1 Mask4 and IF2 Mask4 registers return '1' for reads and should be written '1' .
Operation is not guranteed for a writing '0'.
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