參數(shù)資料
型號(hào)： ML60852
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁(yè)數(shù)： 63/81頁(yè)
文件大?。?/td> 451K
代理商： ML60852
PEDL60852-01
1
Semiconductor
ML60852
63/81
EP1, 2, 4, 5 Status Registers (EP1, 2, 4, 5STAT)
Address
Type
Access type
0 x 61, 62, 64, 65
Bit map
See below
D7
0
0
0
D6
0
0
0
D5
0
0
0
D4
0
0
0
D3
0
0
0
D2
0
0
0
D1
0
0
D0
0
0
After a hardware reset
After a bus reset
Definition
This register is valid only when the corresponding EP has been set for bulk or interrupt transfer.
EP1,2,4,5 Receive packet ready bit (D0): This bit can be read by the local MCU. Also, this bit can be made “0” by
writing a “1” into bit D0. The asserting and de-asserting conditions of
this bit are as given below. The FIFOs of EP1, EP2, EP4, and EP5 have
a 2-layer structure and also there are independent packet ready bits for
layer A and layer B. The switching between these two layers is done
automatically by the ML60852.
Bit name
Asserting condition
When an error-free packet is received
in either layer A or layer B.
Operation when asserted
The local MCU can read the EP1
Receive FIFO. EP1 is locked in the
condition in which data packets have
been received by both layer A and
layer B.
EP1 Receive packet ready (D0)
Bit name
De-asserting condition
When the local MCU has reset
(written a “1” in) the bits of both layer
A and layer B.
Operation when de-asserted
Reception can be made by EP1 when
the bit of either layer A or layer B has
been reset.
EP0 receive packet ready (D0)
EP1,2,4,5 Transmit packet ready bit (D1):This bit can be read by the local MCU. Also, this bit can be made “1” by
writing a “1” into bit D1. The asserting and de-asserting conditions of
this bit are as given below. The FIFO of EP1 has a 2-layer structure and
also there are independent packet ready bits for layer A and layer B. The
switching between these two layers is done automatically by the
ML60852.
Bit name
Asserting condition
Operation when asserted
Transmission can be made from EP1
when either layer A or layer B has
been asserted.
EP1 Transmit packet ready (D1) When the local MCU has set the bits
of both layer A and layer B.
Bit name
De-asserting condition
Operation when de-asserted
EP1 is locked when transmit data has
not been prepared for both layer A
and layer B.
EP1 Transmit packet ready (D1) When an ACK message is received
from the host for the data transmission
to either layer A or layer B.
EP Receive packet
ready (Read/Reset)
EP Transmit packet ready
(Read/Set)
相關(guān)PDF資料
PDF描述
ML6190A Longwave Time Code RF Receiver LSI
ML63187 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min).
ML63189B 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min).
ML63512A 4-Bit Microcontroller with Built-in Level Detector, Melody Circuit, and Comparator,Operating at 0.9 V (Min.)
ML63514A 4-Bit Microcontroller with Built-in Level Detector, Melody Circuit, and Comparator,Operating at 0.9 V (Min.)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML60852A 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller
ML60852ATBZ010 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ML60852ATBZ03A 制造商:ROHM Semiconductor 功能描述:
ML-60-V2/80721 制造商:Thomas & Betts 功能描述:
ML61 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*