參數(shù)資料
型號: ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁數(shù): 25/81頁
文件大?。?/td> 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
25/81
(9) DMA (Direct Memory Access)
It is possible to carry out 8-bit wide or 16-bit wide DMA transfer for the bulk transfer of EP1, EP2, EP4, and EP5,
and for the isochronous transfer of EP4 and EP5. The data bus used is the following:
During 8-bit transfer: AD7 to AD0
During 16-bit transfer: D15 toD8, AD7 to AD0
It is possible to carry out DMA transfers over two channels, Channel 0 and Channel 1. Both demand transfer and
single transfer are supported. The settings of the DMA transfer mode and parameters are done using the DMA
control register and the DMA interval register described later in this manual.
In the demand transfer mode, the
DREQ
pin is asserted when the reading or writing of a data packet becomes
possible. The
DREQ
pin is de-asserted when the transfer of all the data of the receive packets is completed by the
external DMA controller. Therefore, other devices cannot access the local bus during DMA transfer.
On the other hand, in the single transfer mode, the
DREQ
pin is de-asserted at the end of transfer of the number of
bytes (or words) of one transfer, and the other devices can access the local bus during this period.
(10) Power-down
When the ML60852 detects the suspend state on the USB bus, it automatically stops the internal oscillations and
enters the power-down state. When the resume signal is detected on the USB bus, the oscillations are restarted
automatically and the power-down state is released.
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