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參數(shù)資料
| 型號(hào)： | ML60852 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | USB Device Controller |
| 中文描述： | USB設(shè)備控制器 |
| 文件頁數(shù)： | 11/81頁 |
| 文件大?。?/td> | 451K |
| 代理商： | ML60852 |
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PEDL60852-01
1
Semiconductor
ML60852
11/81
Application Interface
Signal
D15: D8
Type
I/O
Assertion
—
Description
Upper byte (MSB) of data bus.
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW.
Chip Select. When this signal is asserted LOW, the ML60852 is selected
and ready to read or write data. This signal is invalid in single address
mode during DMA transfer.
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
Interrupt Request. When this signal is asserted, the ML60852 makes an
interrupt request to the application.
DMA Request. This signal requests the DMA0 to make a DMA transfer.
DMA Request. This signal requests the DMA1 to make a DMA transfer.
DMA Acknowledge Signal for
DREQ0
. This signal, when asserted, enables
accessing FIFOs, without address bus setting.
DMA Acknowledge Signal for
DREQ1
. This signal, when asserted, enables
accessing FIFO, without address bus setting.
When ADSEL is HIGH, the address and
CS
on AD7: AD0 are latched at the
trailing edge of this signal. D+ pull-up resistor connection output when
ADSEL is LOW.
V
CC
potential when bit D3 of SYSCON register is “1”, and high-impedance
when it is “0”.
When ADSEL is LOW, the address is input on A6: A0 and data is input on
AD7: AD0. When ADSEL is HIGH, address and data are multiplexed on
AD7: AD0.
System Reset. When this signal is asserted LOW, the ML60852 is reset.
When the ML60852 is powered on, this signal must be asserted for 1
μ
s or
more.
AD7: AD0
I/O
—
A6: A0
I
—
CS
I
LOW
RD
I
LOW
WR
I
LOW
INTR
O
(Note 1)
DREQ0
DREQ1
O
O
(Note 1)
(Note 1)
DACK0
I
(Note 2)
DACK1
I
(Note 2)
ALE/PUCTL
I or O
HIGH
ADSEL
I
—
RESET
I
LOW
Notes: 1. The assertion can be set by using the assertion select register.
The default is LOW.
2. The assertion can be set by using the assertion select register.
The default is HIGH.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
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